FIGS. 1A-1E show the transistor circuit schematics of conventional 1T1C, 3T, 1T1D, 2T1D, and 3T1D memory cells, respectively. For a detailed description of 1T1C, 3T, 1T1D, 2T1D, and 3T1D memory cells, see, for example, U.S. Pat. No. 3,387,286, entitled “Field-effect Transistor DRAM,” issued Jun. 4, 1968; Karp et al, “A 4096-bit Dynamic MOS RAM,” ISSCC Digest Technical Papers, pp. 10-11, February 1972; U.S. patent application Ser. No. 10/735,061, entitled “Gated Diode Memory Cells,” filed Dec. 11, 2003; and U.S. Pat. No. 7,027,326, entitled “3T1D Memory Cells Using Gated Diodes and Methods of Use Thereof,” issued Apr. 11, 2006. The capacitive storage device of the dynamic memory cell can be a capacitor 104 (typically a planar capacitor or a trench capacitor), a gated diode 118, 165, 185, 194, 199 or the gate capacitor of a transistor 132, 152.
The gate stacks 103, 117, 123, 128, 133, 143, 148, 153, 163, 168, 173, 181, 183, 188, 193, 198 of the transistor(s) 102, 116, 122, 127, 132, 142, 147, 152, 162, 167, 172, 182, 184, 187, 191, 192, 196, 197 in the memory cells 110, 115, 120, 140, 160, 180, 190, 195, (collectively known as memory cells 100) typically comprise a polysilicon gate electrode and a gate dielectric material that is typically silicon dioxide (SiO2), forming a gate stack on a silicon substrate.
These conventional silicon-based dynamic memory cells, which utilize a polysilicon gate electrode and silicon dioxide gate dielectric, require a certain gate oxide thickness (typically 20 Å or above) to hold the electric charges above a threshold level (required for a read operation) in order to maintain sufficient retention time (e.g., in the range of 10 μs-10 ms); otherwise, the charges will leak too quickly through the gate and junction of the transistor(s) and destroy the stored data. This leakage is in addition to the sub-threshold leakage through the source-drain channel of the transistor, which is principally determined by the transistor's threshold voltage and temperature.
In conventional silicon technologies with lithographic dimensions above 130 nm, the gate oxide thickness is typically at least 20 Å and, hence, the retention time is not an issue because the gate oxide leakage in the dynamic memory cells is satisfactorily low. In addition, the transistors utilized in the dynamic memory cells have the same gate oxide thickness and channel length as logic transistors. As lithography is scaled below 130 nm, however, the gate oxide of, for example, logic transistor types is thinned below 20 Å to keep the ratio of channel length and gate oxide thickness more or less constant to maintain a reasonable short channel effect, in line with the rules of classical scaling of silicon technology. As a result of the requirement to maintain the gate oxide thickness at 20 Å or above for dynamic memory cells, the short channel effect cannot be controlled if the channel length and width of the dynamic memory cell transistors is to be reduced. Hence, as the lithography dimension shrinks, the size of the transistors in the dynamic memory cell cannot be scaled together with other transistor types, resulting in a larger transistor area for the dynamic memory cell compared to the other transistors (i.e., the ratio of the memory cell area to logic area increases).
It would be desirable to overcome the limitations of prior art approaches.